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RISC-V: Only use SUBREG if applicable in `riscv_expand_float_scc' 

A subsequent change to enable the processing of conditional moves on a
floating-point condition by `riscv_expand_conditional_move' will cause
`riscv_expand_float_scc' to be called for word-mode target RTX with RV64
targets.  In that case an invalid insn such as:

(insn 25 24 0 (set (reg:DI 141)
        (subreg:SI (reg:DI 143) 0)) -1
     (nil))

would be produced, which would crash the compiler later on.  Since the
output operand of the SET operation to be produced already has the same
mode as the input operand does, just omit the use of SUBREG and assign
directly.

	gcc/
	* config/riscv/riscv.cc (riscv_expand_float_scc): Suppress the
	use of SUBREG if the conditional-set target is word-mode.
This commit is contained in:
Maciej W. Rozycki 2023-11-22 01:18:29 +00:00
parent 5e6903ddd3
commit 7e126d8d0f
1 changed files with 3 additions and 1 deletions
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4
gcc/config/riscv/riscv.cc
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@ -4100,7 +4100,9 @@ riscv_expand_float_scc (rtx target, enum rtx_code code, rtx op0, rtx op1)
riscv_emit_float_compare (&code, &op0, &op1);
rtx cmp = riscv_force_binary (word_mode, code, op0, op1);
riscv_emit_set (target, lowpart_subreg (SImode, cmp, word_mode));
if (GET_MODE (target) != word_mode)
cmp = lowpart_subreg (GET_MODE (target), cmp, word_mode);
riscv_emit_set (target, cmp);
}
/* Jump to LABEL if (CODE OP0 OP1) holds. */