linux/arch/riscv
Icenowy Zheng 8eb8fe67e2
riscv: errata: fix T-Head dcache.cva encoding
The dcache.cva encoding shown in the comments are wrong, it's for
dcache.cval1 (which is restricted to L1) instead.

Fix this in the comment and in the hardcoded instruction.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Guo Ren <guoren@kernel.org>
Tested-by: Drew Fustini <dfustini@baylibre.com>
Link: https://lore.kernel.org/r/20230912072410.2481-1-jszhang@kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-09-12 13:58:40 -07:00
..
boot
configs
errata
include riscv: errata: fix T-Head dcache.cva encoding 2023-09-12 13:58:40 -07:00
kernel riscv: kexec: Align the kexeced kernel entry 2023-09-12 13:58:39 -07:00
kvm
lib
mm Merge patch series "riscv: Introduce KASLR" 2023-09-08 11:25:13 -07:00
net
purgatory
tools
Kbuild
Kconfig
Kconfig.debug
Kconfig.errata riscv: Kconfig.errata: Add dependency for RISCV_SBI in ERRATA_ANDES config 2023-09-08 11:25:28 -07:00
Kconfig.socs
Makefile
Makefile.postlink