Commit Graph

206057 Commits

Author SHA1 Message Date
Vincenzo Palazzo 1f636406e5
nix: add a simple flake nix shell
This commit is specifically targeting enhancements in
Nix support for GCC development. This initiative stems
from the recognized need within our community for a more
streamlined and efficient development process when using Nix.

Signed-off-by: Vincenzo Palazzo <vincenzopalazzodev@gmail.com>
2023-12-05 01:34:15 +01:00
Jason Merrill 4c71855121 c++: fix constexpr noreturn diagnostic
Mentioning a noreturn function does not involve an lvalue-rvalue
conversion.

gcc/cp/ChangeLog:

	* constexpr.cc (potential_constant_expression_1): Fix
	check for loading volatile lvalue.

gcc/testsuite/ChangeLog:

	* g++.dg/cpp0x/constexpr-noreturn1.C: New test.
2023-12-04 18:42:04 -05:00
Andrew Pinski 886f256ce3 MATCH: Fix zero_one_valued_p's convert pattern
While working on PR 111972, I was getting a regression
due to zero_one_valued_p matching a signed 1 bit integer
when it came to convert. This patch fixes that by checking
the outer type too.

Bootstrapped and tested on x86_64-linux-gnu with no regressions.

gcc/ChangeLog:

	* match.pd (zero_one_valued_p): For convert
	make sure type is not a signed 1-bit integer.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
2023-12-04 09:30:53 -08:00
Jeff Law b544ec681b [committed] Fix HImode load mnemonic on microblaze port
The tester recently started failing va-arg-22.c on microblaze-linux:

gcc.c-torture/execute/va-arg-22.c   -O0  (test for excess errors)

It was failing with an undefined reference to "r7" at link time.  This was
ultimately tracked down to a HImode load using (reg+reg) addressing mode, but
which used the lhui instruction instead of lhu.  The "i" means it's supposed to
be (reg+disp) so the assembler tried to interpret "r7" as an immediate/symbol.

The port uses %i<opnum> as an output modifier to select between sh/shi and
various other mnemonics for loads/stores.  The movhi pattern simply failed to
use it for the two cases where it's loading from memory (interestingly enough
it was used for stores).

Clearly we aren't using reg+reg much for HImode loads as this didn't fix
anything else in the testsuite.

gcc/
	* config/microblaze/microblaze.md (movhi): Use %i for half-word
	loads to properly select between lhu/lhui.
2023-12-04 10:06:49 -07:00
Robin Dapp d9b51588e9 RISC-V: testsuite: Remove redundant vector_hw and zvfh_hw.
This replaces the now-redundant vector_hw and zvfh_hw checks in the
testsuite by riscv_v and riscv_zvfh.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c:
	Replace riscv_zvfh_hw with riscv_zvfh.
	* gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c:
	Ditto.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c:
	Ditto.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c: Allow
	overriding N.
	* gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c: Replace
	riscv zvfh_hw with riscv_zvfh.
	* gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c: Ditto.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c: Ditto.
	* lib/target-supports.exp: Remove riscv_vector_hw and
	riscv_zvfh_hw.
2023-12-04 17:06:38 +01:00
Robin Dapp 1067e9d347 RISC-V: Fix two testscases related to -std changes.
Recent -std changes caused testsuite failures.  Fix those by adding
-std=gnu99 and -Wno-incompatible-pointer-types.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/pr112552.c: Add
	-Wno-incompatible-pointer-types.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c:
	Add -std=gnu99.
2023-12-04 17:06:38 +01:00
Robin Dapp cdb34bf5dd RISC-V: Fix rawmemchr implementation.
This fixes a bug in the rawmemchr implementation by incrementing the
source address by vl * element_size instead of just vl.

This is normally harmless as we will just scan the same region more than
once but, in combination with an older qemu version, will lead to
an execution failure in SPEC2017.

gcc/ChangeLog:

	* config/riscv/riscv-string.cc (expand_rawmemchr): Increment
	source address by vl * element_size.
2023-12-04 16:24:19 +01:00
Robin Dapp 4ae5a7336a RISC-V: Rename and unify stringop strategy handling.
In preparation for the vectorized strlen and strcmp support this NFC
patch unifies the stringop strategy handling a bit.  The "auto"
strategy now is a combination of scalar and vector and an expander
should try the strategies in their preferred order.

For the block_move expander this patch does just that.

gcc/ChangeLog:

	* config/riscv/riscv-opts.h (enum riscv_stringop_strategy_enum):
	Rename...
	(enum stringop_strategy_enum): ... to this.
	* config/riscv/riscv-string.cc (riscv_expand_block_move): New
	wrapper expander handling the strategies and delegation.
	(riscv_expand_block_move_scalar): Rename function and make
	static.
	(expand_block_move): Remove strategy handling.
	* config/riscv/riscv.md: Call expander wrapper.
	* config/riscv/riscv.opt: Rename.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/cpymem-strategy-1.c: Change to
	-mstringop-strategy.
	* gcc.target/riscv/rvv/base/cpymem-strategy-2.c: Ditto.
	* gcc.target/riscv/rvv/base/cpymem-strategy-3.c: Ditto.
	* gcc.target/riscv/rvv/base/cpymem-strategy-4.c: Ditto.
	* gcc.target/riscv/rvv/base/cpymem-strategy-5.c: Ditto.
2023-12-04 16:23:56 +01:00
Richard Biener 0c2ea80a4f middle-end/112785 - guard against last_clique overflow
The PR shows that we'll ICE eventually when last_clique wraps.  The
following avoids this by refusing to hand out new cliques after
exhausting them.  We then use zero (no clique) as conservative
fallback.

	PR middle-end/112785
	* function.h (get_new_clique): New inline function handling
	last_clique overflow.
	* cfgrtl.cc (duplicate_insn_chain): Use it.
	* tree-cfg.cc (gimple_duplicate_bb): Likewise.
	* tree-inline.cc (remap_dependence_clique): Likewise.
2023-12-04 15:33:58 +01:00
Christoph Müllner 82576a6e77 RISC-V: Document optimization parameter riscv-strcmp-inline-limit
This patch documents the optimization parameter
riscv-strcmp-inline-limit, which can be used to tweak the behaviour
of -minline-strcmp and -minline-strncmp.

gcc/ChangeLog:

	PR target/112650
	* doc/invoke.texi: Document riscv-strcmp-inline-limit.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-12-04 14:56:14 +01:00
Juzhe-Zhong 018ba3ac95 RISC-V: Fix overlap group incorrect overlap on v0
In serious high register pressure case (appended in this patch):

We see vluxei8.v       v0,(s1),v1,v0.t which is not allowed.
Since according to RVV ISA:

+;; The destination vector register group for a masked vector instruction cannot overlap the source mask register (v0),
+;; unless the destination vector register is being written with a mask value (e.g., compares) or the scalar result of a reduction.

Such case doesn't have spillings, however, we expect such case should be spilled and reload data.

The rootcause is I made a mistake in previous patch on matching dest operand and mask operand constraints:

dest: "=vr"
mask: "vmWc1"

After this patch:

dest: "vd,vr"
mask: "vm,Wc1"

make EEW widening pattern are same as other instruction patterns.

	PR target/112431

gcc/ChangeLog:

	* config/riscv/vector.md: Fix incorrect overlap in v0.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/pr112431-34.c: New test.
2023-12-04 21:47:51 +08:00
Juzhe-Zhong 27fde325d6 RISC-V: Support highest-number regno overlap for widen ternary
Consider this example:

#include "riscv_vector.h"
void
foo6 (void *in, void *out)
{
  vfloat64m8_t accum = __riscv_vle64_v_f64m8 (in, 4);
  vfloat64m4_t high_eew64 = __riscv_vget_v_f64m8_f64m4 (accum, 1);
  vint64m4_t high_eew64_i = __riscv_vreinterpret_v_f64m4_i64m4 (high_eew64);
  vint32m4_t high_eew32_i = __riscv_vreinterpret_v_i64m4_i32m4 (high_eew64_i);
  vfloat32m4_t high_eew32 = __riscv_vreinterpret_v_i32m4_f32m4 (high_eew32_i);
  vfloat64m8_t result = __riscv_vfwnmsac_vf_f64m8 (accum, 64, high_eew32, 4);
  __riscv_vse64_v_f64m8 (out, result, 4);
}

Before this patch:

foo6:                                   # @foo6
        vsetivli        zero, 4, e32, m4, ta, ma
        vle64.v v8, (a0)
        lui     a0, 272384
        fmv.w.x fa5, a0
        vmv8r.v v16, v8
        vfwnmsac.vf     v16, fa5, v12
        vse64.v v16, (a1)
        ret

After this patch:

foo6:
.LFB5:
	.cfi_startproc
	lui	a5,%hi(.LC0)
	flw	fa5,%lo(.LC0)(a5)
	vsetivli	zero,4,e32,m4,ta,ma
	vle64.v	v8,0(a0)
	vfwnmsac.vf	v8,fa5,v12
	vse64.v	v8,0(a1)
	ret

	PR target/112431

gcc/ChangeLog:

	* config/riscv/vector.md: Add highest-number overlap support.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/pr112431-37.c: New test.
	* gcc.target/riscv/rvv/base/pr112431-38.c: New test.
2023-12-04 21:36:00 +08:00
Richard Biener 80d67d8f68 tree-optimization/112818 - re-instantiate vector type size check for bswap
For __builtin_bswap vectorization we still require an equal vector
type size.  Re-instantiate that check.

	PR tree-optimization/112818
	* tree-vect-stmts.cc (vectorizable_bswap): Check input and
	output vector types have the same size.

	* gcc.dg/vect/pr112818.c: New testcase.
2023-12-04 14:26:12 +01:00
Juzhe-Zhong 969d4e25e7 RISC-V: Rename bug-01.C to bug-1.C
Rename test to make RVV tests consistent, prepare for the following patches.

gcc/testsuite/ChangeLog:

	* g++.target/riscv/rvv/autovec/bug-01.C: Moved to...
	* g++.target/riscv/rvv/autovec/bug-1.C: ...here.
2023-12-04 20:06:56 +08:00
Richard Biener de0ab339a7 tree-optimization/112827 - corrupt SCEV cache during SCCP
The following avoids corrupting the SCEV cache by my last change
to propagate constant final values immediately.  The easiest fix
is to keep a dead initialization around.

	PR tree-optimization/112827
	* tree-scalar-evolution.cc (final_value_replacement_loop):
	Do not release SSA name but keep a dead initialization around.

	* gcc.dg/torture/pr112827-1.c: New testcase.
	* gcc.dg/torture/pr112827-2.c: Likewise.
2023-12-04 12:53:55 +01:00
Juzhe-Zhong 7804b4e24c RISC-V: Remove earlyclobber from widen reduction
Since the destination of reduction is not a vector register group, there
is no need to apply overlap constraint.

Also confirm Clang:

The mir in LLVM has early clobber:
early-clobber %49:vrm2 = PseudoVWADD_VX_M1 $noreg(tied-def 0), killed %17:vr, %48:gpr, %0:gprnox0, 3, 0; example.c:59:24

The mir in LLVM doesn't have early clobber:
%48:vr = PseudoVWREDSUM_VS_M2_E8 $noreg(tied-def 0), %17:vrm2, killed %33:vr, %0:gprnox0, 3, 1; example.c:60:26

And also confirm both:

vwredsum.vs     v24, v8, v24 and vwredsum.vs     v8, v8, v24 all legal on LLVM.

Align with LLVM and honor RISC-V V spec, remove earlyclobber.

Before this patch:

	vwredsum.vs     v8,v24,v8
        vwredsum.vs     v7,v22,v7
        vwredsum.vs     v6,v20,v6
        vwredsum.vs     v5,v18,v5
        vwredsum.vs     v4,v16,v4
        vwredsum.vs     v3,v14,v3
        vwredsum.vs     v2,v12,v2
        vwredsum.vs     v1,v10,v1
        vmv1r.v v9,v8
        vwredsum.vs     v9,v24,v9
        vmv1r.v v24,v7
        vwredsum.vs     v24,v22,v24
        vmv1r.v v22,v6
        vwredsum.vs     v22,v20,v22
        vmv1r.v v20,v5
        vwredsum.vs     v20,v18,v20
        vmv1r.v v18,v4
        vwredsum.vs     v18,v16,v18
        vmv1r.v v16,v3
        vwredsum.vs     v16,v14,v16
        vmv1r.v v14,v2
        vwredsum.vs     v14,v12,v14
        vmv1r.v v12,v1
        vwredsum.vs     v12,v10,v12

After this patch:

	vfwredusum.vs	v17,v12,v17
	vfwredusum.vs	v18,v10,v18
	vfwredusum.vs	v15,v26,v15
	vfwredusum.vs	v16,v24,v16
	vfwredusum.vs	v12,v12,v17
	vfwredusum.vs	v10,v10,v18
	vfwredusum.vs	v13,v6,v20
	vfwredusum.vs	v11,v8,v19
	vfwredusum.vs	v6,v6,v13
	vfwredusum.vs	v8,v8,v11
	vfwredusum.vs	v7,v4,v21
	vfwredusum.vs	v9,v2,v22
	vfwredusum.vs	v14,v26,v15
	vfwredusum.vs	v1,v24,v16
	vfwredusum.vs	v4,v4,v7
	vfwredusum.vs	v2,v2,v9

Same behavior as LLVM, and honor RISC-V V spec.

	PR target/112431

gcc/ChangeLog:

	* config/riscv/vector.md: Remove earlyclobber from widen reduction.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/pr112431-35.c: New test.
	* gcc.target/riscv/rvv/base/pr112431-36.c: New test.
2023-12-04 18:45:10 +08:00
Indu Bhagat b6abc5dbfa BTF: fix PR debug/112656
PR debug/112656 - btf: function prototypes generated with name

With this patch, all BTF_KIND_FUNC_PROTO will appear anonymous in the
generated BTF section.

As noted in the discussion in the bugzilla, the number of
BTF_KIND_FUNC_PROTO types output varies across targets (BPF with -mco-re
vs non-BPF targets).  Hence the check in the test case merely checks
that all BTF_KIND_FUNC_PROTO appear anonymous.

gcc/ChangeLog:

	PR debug/112656
	* btfout.cc (btf_asm_type): Fixup ctti_name for all
	BTF types of kind BTF_KIND_FUNC_PROTO.

gcc/testsuite/ChangeLog:

	PR debug/112656
	* gcc.dg/debug/btf/btf-function-7.c: New test.
2023-12-04 02:00:37 -08:00
Indu Bhagat 9b6e2cb7e6 BTF: fix PR debug/112768
PR debug/112768 - btf: fix asm comment output for BTF_KIND_FUNC* kinds

The patch adds a small function to abstract out the detail and return
the name of the type.  The patch also fixes the issue of BTF_KIND_FUNC
appearing in the comments with a 'null' string.

For btf-function-6.c testcase, after the patch:

        .long   0       # TYPE 2 BTF_KIND_FUNC_PROTO ''
        .long   0xd000002       # btt_info: kind=13, kflag=0, vlen=2
        .long   0x1     # btt_type: (BTF_KIND_INT 'int')
        .long   0       # farg_name
        .long   0x1     # farg_type: (BTF_KIND_INT 'int')
        .long   0       # farg_name
        .long   0x1     # farg_type: (BTF_KIND_INT 'int')
        .long   0       # TYPE 3 BTF_KIND_FUNC_PROTO ''
        .long   0xd000001       # btt_info: kind=13, kflag=0, vlen=1
        .long   0x1     # btt_type: (BTF_KIND_INT 'int')
        .long   0x68    # farg_name
        .long   0x1     # farg_type: (BTF_KIND_INT 'int')
        .long   0x5     # TYPE 4 BTF_KIND_FUNC 'extfunc'
        .long   0xc000002       # btt_info: kind=12, kflag=0, linkage=2
        .long   0x2     # btt_type: (BTF_KIND_FUNC_PROTO '')
        .long   0xd     # TYPE 5 BTF_KIND_FUNC 'foo'
        .long   0xc000001       # btt_info: kind=12, kflag=0, linkage=1
        .long   0x3     # btt_type: (BTF_KIND_FUNC_PROTO '')

gcc/ChangeLog:

	PR debug/112768
	* btfout.cc (get_btf_type_name): New definition.
	(btf_collect_datasec): Update dtd_name to the original type name
	string.
	(btf_asm_type_ref): Use the new get_btf_type_name function
	instead.
	(btf_asm_type): Likewise.
	(btf_asm_func_type): Likewise.

gcc/testsuite/ChangeLog:

	PR debug/112768
	* gcc.dg/debug/btf/btf-function-6.c: Empty string expected with
	BTF_KIND_FUNC_PROTO.
2023-12-04 01:57:25 -08:00
Pan Li 462ccc3b9d RISC-V: Add test case for bug PR112813
The bugzilla 112813 has been fixed recently, add below test
case for the bug.

	PR target/112813

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/vsetvl/pr112813-1.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
2023-12-04 16:11:10 +08:00
Jakub Jelinek 4586d7d0a9 i386: Fix rtl checking ICE in ix86_elim_entry_set_got [PR112837]
The following testcase ICEs with RTL checking, because it sets if
XINT (SET_SRC (set), 1) is UNSPEC_SET_GOT without checking if SET_SRC (set)
is actually an UNSPEC, so any time we see any other insn with PARALLEL
and a SET in it which is not an UNSPEC we ICE during RTL checking or
access there some other union member as if it was an rt_int.
The rest is just small cleanup.

2023-12-04  Jakub Jelinek  <jakub@redhat.com>

	PR target/112837
	* config/i386/i386.cc (ix86_elim_entry_set_got): Before checking
	for UNSPEC_SET_GOT check that SET_SRC is UNSPEC.  Use SET_SRC and
	SET_DEST macros instead of XEXP, rename vec variable to set.

	* gcc.dg/pr112837.c: New test.
2023-12-04 09:01:09 +01:00
Jakub Jelinek 994d6dc644 i386: Fix up signbit<mode>2 expander [PR112816]
The following testcase ICEs, because the signbit<mode>2 expander uses an
explicit SUBREG in the pattern around match_operand with register_operand
predicate.  If we are unlucky enough that expansion tries to expand it
with some SUBREG as operands[1], we have two nested SUBREGs in the IL,
which is not valid and causes ICE later.

2023-12-04  Jakub Jelinek  <jakub@redhat.com>

	PR target/112816
	* config/i386/sse.md (signbit<mode>2): Force operands[1] into a REG.

	* gcc.target/i386/sse2-pr112816.c: New test.
2023-12-04 09:00:18 +01:00
Jakub Jelinek b6c78feea0 c++: #pragma GCC unroll C++ fixes [PR112795]
foo in the unroll-5.C testcase ICEs because cp_parser_pragma_unroll
during parsing calls maybe_constant_value unconditionally, which is
fine if !processing_template_decl, but can ICE otherwise.

While just calling fold_non_dependent_expr there instead could be enough
to fix the ICE (and I guess the right thing to do for backports if any),
I don't see a reason why we couldn't handle a dependent #pragma GCC unroll
argument as well, the unrolling isn't done in the FE and all the middle-end
cares about is that ANNOTATE_EXPR has a 1..65534 last operand when it is
annot_expr_unroll_kind.

So, the following patch changes all the unsigned short unroll arguments
to tree unroll (and thus avoids the tree -> unsigned short -> tree
conversions), does the type and value checking during parsing only if
the argument isn't dependent and repeats it during instantiation.

2023-12-04  Jakub Jelinek  <jakub@redhat.com>

	PR c++/112795
gcc/cp/
	* cp-tree.h (cp_convert_range_for): Change UNROLL type from
	unsigned short to tree.
	(finish_while_stmt_cond, finish_do_stmt, finish_for_cond): Likewise.
	* parser.cc (cp_parser_statement): Pass NULL_TREE rather than 0 to
	cp_parser_iteration_statement UNROLL argument.
	(cp_parser_for, cp_parser_c_for): Change UNROLL type from
	unsigned short to tree.
	(cp_parser_range_for): Likewise.  Set RANGE_FOR_UNROLL to just UNROLL
	rather than build_int_cst from it.
	(cp_convert_range_for, cp_parser_iteration_statement): Change UNROLL
	type from unsigned short to tree.
	(cp_parser_omp_loop_nest): Pass NULL_TREE rather than 0 to
	cp_parser_range_for UNROLL argument.
	(cp_parser_pragma_unroll): Return tree rather than unsigned short.
	If parsed expression is type dependent, just return it, don't diagnose
	issues with value if it is value dependent.
	(cp_parser_pragma): Change UNROLL type from unsigned short to tree.
	* semantics.cc (finish_while_stmt_cond): Change UNROLL type from
	unsigned short to tree.  Build ANNOTATE_EXPR with UNROLL as its last
	operand rather than build_int_cst from it.
	(finish_do_stmt, finish_for_cond): Likewise.
	* pt.cc (tsubst_stmt) <case RANGE_FOR_STMT>: Change UNROLL type from
	unsigned short to tree and set it to RECUR on RANGE_FOR_UNROLL (t).
	(tsubst_expr) <case ANNOTATE_EXPR>: For annot_expr_unroll_kind repeat
	checks on UNROLL value from cp_parser_pragma_unroll.
gcc/testsuite/
	* g++.dg/ext/unroll-5.C: New test.
	* g++.dg/ext/unroll-6.C: New test.
2023-12-04 08:59:15 +01:00
Feng Wang 9448428b68 RISC-V: Update crypto vector ISA info with latest spec
This patch add the Zvkb subset of crypto vector extension. The
corresponding test cases have aslo been modified.

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc: Add zvkb ISA info.
	* config/riscv/riscv.opt: Add Mask(ZVKB)

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zvkn-1.c: Replace zvbb with zvkb.
	* gcc.target/riscv/zvkn.c:   Ditto.
	* gcc.target/riscv/zvknc-1.c:Ditto.
	* gcc.target/riscv/zvknc-2.c:Ditto.
	* gcc.target/riscv/zvknc.c:  Ditto.
	* gcc.target/riscv/zvkng-1.c:Ditto.
	* gcc.target/riscv/zvkng-2.c:Ditto.
	* gcc.target/riscv/zvkng.c:  Ditto.
	* gcc.target/riscv/zvks-1.c: Ditto.
	* gcc.target/riscv/zvks.c:   Ditto.
	* gcc.target/riscv/zvksc-1.c:Ditto.
	* gcc.target/riscv/zvksc-2.c:Ditto.
	* gcc.target/riscv/zvksc.c:  Ditto.
	* gcc.target/riscv/zvksg-1.c:Ditto.
	* gcc.target/riscv/zvksg-2.c:Ditto.
	* gcc.target/riscv/zvksg.c:  Ditto.
2023-12-04 07:07:26 +00:00
Fei Gao fc98a41c8d prefer Zicond primitive semantics to SFB
Move Zicond md files ahead of SFB to recognize Zicond first.

Take the following case for example.

CFLAGS: -mtune=sifive-7-series -march=rv64gc_zicond -mabi=lp64d

long primitiveSemantics_00(long a, long b) { return a == 0 ? 0 : b; }

before patch:
primitiveSemantics_00:
	bne	a0,zero,1f	# movcc
	mv	a1,zero
1:
	mv	a0,a1
	ret

after patch:
primitiveSemantics_00:
	czero.eqz	a0,a1,a0
	ret

Co-authored-by: Xiao Zeng<zengxiao@eswincomputing.com>

gcc/ChangeLog:

	* config/riscv/riscv.md (*mov<GPR:mode><X:mode>cc):move to sfb.md
	* config/riscv/sfb.md: New file.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zicond-sfb-primitiveSemantics.c: New test.
2023-12-04 06:55:47 +00:00
Kito Cheng ba94969bad RISC-V: Add sifive-x280 to -mcpu
x280 is one of SiFive core, and it release for a while, also
upstream LLVM already support that.

[1] https://www.sifive.com/cores/intelligence-x280

gcc/ChangeLog:

	* config/riscv/riscv-cores.def: Add sifive-x280.
	* doc/invoke.texi (RISC-V Options): Add sifive-x280

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/mcpu-sifive-x280.c: New test.
2023-12-04 14:38:10 +08:00
Kito Cheng 9e12010b5e RISC-V: Refactor riscv_implied_info_t to make it able to handle conditional implication [NFC]
RISC-V ISA implication rules become little bit complicated than before,
it may come with condition, so this commit extend the capability of
riscv_implied_info_t, also make it more...C++ize.

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc (riscv_implied_predicator_t): New.
	(riscv_implied_info_t::riscv_implied_info_t): New.
	(riscv_implied_info_t::match): New.
	(riscv_implied_info): New entry for zcf.
	(riscv_subset_list::handle_implied_ext): Use
	riscv_implied_info_t::match.
	(riscv_subset_list::check_implied_ext): Ditto.
	(riscv_subset_list::handle_combine_ext): Ditto.
	(riscv_subset_list::parse): Move zcf implication handling to
	riscv_implied_infos.
2023-12-04 14:38:10 +08:00
Kito Cheng 26b1599d83 RISC-V: Refine riscv_subset_list::parse [NFC]
Extract the logic of checking conflict extensions to a standard alone
function, prepare to add more checking logic.

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc
	(riscv_subset_list::check_conflict_ext): New.
	(riscv_subset_list::parse): Move checking conflict ext. to
	check_conflict_ext.
	* config/riscv/riscv-subset.h:
	Add riscv_subset_list::check_conflict_ext.
2023-12-04 14:34:41 +08:00
Hu, Lin1 88029286c3 i386: Fix CPUID of USER_MSR.
gcc/ChangeLog:

	* common/config/i386/cpuinfo.h (get_available_features): Move USER_MSR
	to the correct location.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/user_msr-1.c: Correct the MSR index for give the user
	an proper example.
2023-12-04 10:02:13 +08:00
Gaius Mulley 4e5f5a8ae8 PR modula2/112825: modula2 builds target objects as part of all-gcc
This patch fixes the PR modula2/112825 which fails if the target
assembler is not present on the host.  This can be seen if the
build invokes make all-gcc.  m2 should not attempt to generate
target libraries when performing make all-gcc.

Prior to this patch it generated build/gcc/m2/gm2-libs/SYSTSEM.def
using the script gcc/m2/tools-src/makeSystem (and gm2 -c).
makeSystem should exec gm2 -S instead (and other flags)
to generate the list of target data types without requiring any
target tools.  The target types emitted are textually converted
into SYSTEM.def.

gcc/m2/ChangeLog:

	PR modula2/112825
	* tools-src/makeSystem: Change all occurrences of -c to -S.

Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2023-12-04 01:35:46 +00:00
Juzhe-Zhong d3544cea63 RISC-V: Robostify the W43, W86, W87 constraint enabled attribute
Committed as it is obvious fix.

gcc/ChangeLog:

	* config/riscv/riscv.md: Rostify the constraints.
2023-12-04 09:25:43 +08:00
chenxiaolong 1f48786d86 LoongArch: Add intrinsic function descriptions for LSX and LASX instructions to doc.
gcc/ChangeLog:

	* doc/extend.texi: Add information about the intrinsic function of the vector
	instruction.
2023-12-04 09:21:19 +08:00
GCC Administrator 833819e75a Daily bump. 2023-12-04 00:16:38 +00:00
Jakub Jelinek 4c0dc30099 testsuite: Fix up gcc.target/aarch64/pr112406.c for modern C [PR112406]
On Fri, Nov 17, 2023 at 02:04:01PM +0100, Robin Dapp wrote:
> > Yes, your version is also OK.
>
> The attached was bootstrapped and regtested on aarch64, x86 and
> regtested on riscv.  Going to commit it later unless somebody objects.

Unfortunately the aarch64/pr112406.c was reduced too much and is rejected
since the switch to modern C patchset.

The following patch fixes that, I've verified the testcase
before/after the changes still ICEs in r14-5563 and doesn't with
r14-5564 and after the changes compiles fine with even latest trunk.
Everything admittedly with a cross-compiler, but that shouldn't change
anything.

Note, one of the modern C changes is that at least when people use
cvise/creduce/delta scripts which ensure no further errors are introduced
during the reduction then expected originally such reductions will not
appear anymore.

2023-12-03  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/112406
	* gcc.target/aarch64/pr112406.c (MagickPixelPacket): Add missing
	semicolon.
	(GetImageChannelMoments_image): Avoid using implicit int.
	(SetMagickPixelPacket): Use void return type instead of implicit int.
	(GetImageChannelMoments): Likewise.  Use __builtin_atan instead of
	atan.
2023-12-03 20:03:27 +01:00
Jakub Jelinek eef6aea305 lower-bitint: Fix up lower_addsub_overflow [PR112807]
lower_addsub_overflow uses handle_cast or handle_operand to extract current
limb from the operands.  Both of those functions heavily assume that they
return a large or huge BITINT_TYPE.  The problem in the testcase is that
this is violated.  Normally, lower_addsub_overflow isn't even called if
neither the return's type element type nor any of the operand is large/huge
BITINT_TYPE (on x86_64 129+ bits), for middle BITINT_TYPE (on x86_64 65-128
bits) some other code casts such operands to {,unsigned }__int128.
In the testcase the result is complex unsigned, so small, but one of the
arguments is _BitInt(256), so lower_addsub_overflow is called.  But
range_for_prec asks the ranger for ranges of the operands and in this
case the first argument has [0, 0xffffffff] range and second [-2, 1], so
unsigned 32-bit and signed 2-bit, and in such case the code for
handle_operand/handle_cast purposes would use the _BitInt(256) type for the
first operand (ok), but because prec3 aka maximum of result precision and
the VRP computes ranges of the arguments is 32, use cast to 32-bit
BITINT_TYPE, which is why it didn't work correctly.
The following patch ensures that in such cases we use handle_cast to the
type of the other argument.

Perhaps incrementally, we could try to optimize this in an earlier phase,
see that while the .{ADD,SUB}_OVERFLOW has large/huge _BitInt argument, as
ranger says it fits into a smaller type, add a cast of the larger argument
to the smaller precision type in which it fits.  Either in
gimple_lower_bitint, or match.pd.  An argument for the latter is that e.g.
complex unsigned .ADD_OVERFLOW (unsigned_long_long_arg, unsigned_arg)
where ranger says unsigned_long_long_arg fits into unsigned 32-bit could
be also more efficient as
.ADD_OVERFLOW ((unsigned) unsigned_long_long_arg, unsigned_arg)

2023-12-03  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/112807
	* gimple-lower-bitint.cc (bitint_large_huge::lower_addsub_overflow):
	When choosing type0 and type1 types, if prec3 has small/middle bitint
	kind, use maximum of type0 and type1's precision instead of prec3.

	* gcc.dg/bitint-46.c: New test.
2023-12-03 17:54:03 +01:00
Saurabh Jha 8bc06e8302 testsuite: Fix up pr112337.c test
gcc/testsuite/ChangeLog:

	* gcc.target/arm/mve/pr112337.c: Use int32_t instead of int.
2023-12-03 16:15:24 +00:00
Pan Li 806789e6da RISC-V: Fix typo in test abi configuration
It should be -mabi=lp64d instead of -mabi=lp64, committed in as obvious.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/pr112743-1.c: Fix typo.
	* gcc.target/riscv/rvv/base/pr112743-2.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>
2023-12-03 22:17:30 +08:00
Jeff Law f37744662c [committed] Fix gnu23-builtins-no-dfp
Last patch for the night.  There's still a bit of minor fallout left in GCC
(loongarch testsuite for example).  But things are looking good on the targets
I test.  The plan is to start submitting the various newlib/libgloss fixes
tomorrow.

Anyway, this test was the one I was most concerned about.  Basically we're
testing that on a !dfp target that the builtins are not available.  It expects
a warning, but gets an error by default now.  I just changed the test to use
-fpermissive, so that the test behaves as it did previously.

Pushed to the trunk.

gcc/testsuite
	* gcc.dg/gnu23-builtins-no-dfp-1.c: Add -fpermissive.
2023-12-02 22:54:46 -07:00
Jeff Law 4cef6daf40 [committed] Fix build of libgcc on ports using FDPIC
read_encoded_value_with_base has an ifdef'd code path conditional on __FDPIC__
which was calling _Unwind_gnu_Find_got without a prototype.  This naturally
caused various build failures.

This adds a suitable prototype.

Pushed to the trunk.

libgcc

	* unwind-pe.h (_Unwind_gnu_Find_got): Add prototype.
2023-12-02 22:45:48 -07:00
Jeff Law 3da08ffa6d [committed] Fix pr65369.c
There's a caller/callee type mismatch in this test that shows up on targets
where ints are something other than 32 bit types.

Based on reviewing the original bug report, the fix and the part of the test
this fixes, I'm reasonably confident this hasn't compromised the test.

gcc/testsuite
	* gcc.c-torture/execute/pr65369.c: Fix type mismatch.
2023-12-02 22:40:41 -07:00
Jeff Law d5c823b033 [committed] Fix comp-goto-1.c on 16 bit targets
I don't remember what port triggered this, but it's obviously that
comp-goto-1.c needs to be fixed.

Basically the test has two implementations.  One is just a dummy with no return
value on main() triggering the new errors.

gcc/testsuite
	* gcc.c-torture/execute/comp-goto-1.c: Fix return value of main for
	16 bit targets.
2023-12-02 22:32:22 -07:00
Jeff Law 595c695216 [committed] Fix a few arc tests
Similar to others.  Where it's easy to fix the implicit types or add prototypes
I did.  One was just ugly and I didn't want to think too hard, so I just added
-fpermissive.

Pushed to the trunk.

gcc/testsuite
	* gcc.target/arc/lra-1.c: Fix missing prototypes and implicit
	types in variable definitions.
	* gcc.target/arc/pic-1.c: Similarly.
	* gcc.target/arc/pr9001191897.c: Similarly.
	* gcc.target/arc/pr9001195952.c: Add -fpermissive.
2023-12-02 22:17:57 -07:00
Jeff Law 2280317c37 [committed] Fix nios2 tests
The nios2 port has two tests that are affected by the recent changes.  In
cdx-ldstwm-1.c it was easiest to just add -fpermissive.  for cdx-ldstwm-2.c
adding an prototype for exit and abort is all that's needed.

gcc/testsuite
	* gcc.target/nios2/cdx-ldstwm-1.c: Add -fpermissive.
	* gcc.target/nios2/cdx-ldstwm-2.c: Add prototypes fro abort and exit.
2023-12-02 22:14:02 -07:00
Jeff Law f1fdd2839c [committed] Fix rx build failure in libgcc
The rx port has a bunch of what I presume are ABI compatibility functions in
libgcc.  Those compatibility functions routines such as __eqdf2 from libgcc,
but without a prototype.  This patch adds the missing prototypes.

libgcc/
	* config/rx/rx-abi-functions.c (__ltdf2, __gtdf2): Add prototype.
	(__ledf2, __gedf2, __eqdf2, __nedf2): Likewise.
	(__ltsf2, __gtsf2, __lesf2, __gesf2, __eqsf2, __nesf2): Likewise.
2023-12-02 22:07:59 -07:00
Jeff Law 622c535667 [committed] Fix minor testsuite problems on H8 after C99 changes
Two minor regressions on the H8 were triggered by the C99 changes.  First
pr58400.c has several functions without prototypes.  I just added -fpermissive
to that test.  Second pr17306-2.c has a single call to an unprototyped function
for which I added the prototype.

These are both H8 specific tests.

gcc/testsuite
	* gcc.target/h8300/pr58400.c: Add -fpermissive.
	* gcc.target/h8300/pr17306-2.c: Add missing prototype.
2023-12-02 22:03:28 -07:00
Jeff Law 870b63fe71 [committed] Fix frv build after C99 changes
Two issues prevent the frv-elf port from building after the C99 changes.  First
the trampoline code emitted into libgcc has calls to exit, but no prototype.
Adding a trivial prototype for exit() into the macro fixes that little goof.

Second, frvbegin.c has a call to atexit, so a quick prototype is added into
frvbegin.c to fix that problem.

That's enough to get the compiler building again.

gcc/
	* config/frv/frv.h (TRANSFER_FROM_TRAMPOLINE): Add prototype for exit.

libgcc/
	* config/frv/frvbegin.c (atexit): Add prototype.
2023-12-02 21:54:36 -07:00
GCC Administrator 04d4a4943a Daily bump. 2023-12-03 00:16:41 +00:00
Alexandre Oliva f4dd941684 libsupc++: try cxa_thread_atexit_impl at runtime
g++.dg/tls/thread_local-order2.C fails when the toolchain is built for
a platform that lacks __cxa_thread_atexit_impl, even if the program is
built and run using that toolchain on a (later) platform that offers
__cxa_thread_atexit_impl.

This patch adds runtime testing for __cxa_thread_atexit_impl on
platforms that support weak symbols.


for  libstdc++-v3/ChangeLog

	* libsupc++/atexit_thread.cc [__GXX_WEAK__]: Add dynamic
	detection of __cxa_thread_atexit_impl.
2023-12-02 14:14:02 -03:00
Harald Anlauf 27ce74fa23 Fortran: deferred-length character optional dummy arguments [PR93762,PR100651]
gcc/fortran/ChangeLog:

	PR fortran/93762
	PR fortran/100651
	* trans-array.cc (gfc_trans_deferred_array): Add presence check
	for optional deferred-length character dummy arguments.
	* trans-expr.cc (gfc_conv_missing_dummy): The character length for
	deferred-length dummy arguments is passed by reference, so that
	its value can be returned.  Adjust handling for optional dummies.

gcc/testsuite/ChangeLog:

	PR fortran/93762
	PR fortran/100651
	* gfortran.dg/optional_deferred_char_1.f90: New test.
2023-12-02 15:14:20 +01:00
Richard Sandiford df4643f90c attribs: Namespace-aware lookup_attribute_spec
attribute_ignored_p already used a namespace-aware query
to find the attribute_spec for an existing attribute:

      const attribute_spec *as = lookup_attribute_spec (TREE_PURPOSE (attr));

This patch does the same for other callers in the file.

gcc/
	* attribs.cc (comp_type_attributes): Pass the full TREE_PURPOSE
	to lookup_attribute_spec, rather than just the name.
	(remove_attributes_matching): Likewise.
2023-12-02 13:49:55 +00:00
Richard Sandiford f8135a5aef attribs: Consider namespaces when comparing attributes
decl_attributes and comp_type_attributes both had code that
iterated over one list of attributes and looked for coresponding
attributes in another list.  This patch makes those lookups
namespace-aware.

gcc/
	* attribs.cc (find_same_attribute): New function.
	(decl_attributes, comp_type_attributes): Use it when looking
	up one list's attributes in another list.
2023-12-02 13:49:54 +00:00